1. Field of the Invention
The present invention relates to a semiconductor memory device that performs data input to and data output from memory cells in bursts, and particularly to a semiconductor memory device that is provided with an operation mode in which data that are read from memory cells are outputted to the outside without being latched.
2. Description of the Related Art
In recent years, the operating speed of CPUs (Central Processing Units) has been increasing with each year along with the miniaturization of LSI (Large-Scale Integrated circuits). However, in spite of the increase in storage capacity of semiconductor memory devices such as DRAM (Dynamic Random Access Memory), the fact remains that greater memory capacity is accompanied by a corresponding increase in the wiring length, and the speed of these memory devices lags behind CPU speeds due to the delay resulting from the charging and discharging of word lines and bit lines.
This state has led to the implementation of various designs to realize an apparent increase in speed of the semiconductor memory device. One method that has been considered is using serial exchange of data with the outside of the semiconductor memory device while using parallel transfer of data between memory cells and other circuits inside the semiconductor memory device. Alternatively, it is possible to apply a DDR (Double Data Rate) technique by which input and output of data are performed at both the rise and fall of the basic clocks in the system that uses the semiconductor memory device, whereby input and output data are divided between two phases, the input and output operations of each phase are performed by parallel processing in the semiconductor memory device, and an internal processing period that corresponds to double the data input/output period is secured for the input/output data of each phase.
This type of semiconductor memory device may also be provided with several modes when reading serial data to the outside of the semiconductor memory device. As one of these modes, there is a mode in which, after once latching all bits of parallel data that have been simultaneously read from memory cells, the latched parallel data are then serially outputted to the outside (hereinbelow referred to as xe2x80x9clatch modexe2x80x9d). In addition to this latch mode, there is a mode in which, to enable a shorter access time than that of latch mode, only the bit of the read parallel data that are to be outputted to outside the semiconductor memory device first are outputted xe2x80x9cthroughxe2x80x9d without latching (hereinbelow referred to as xe2x80x9cthrough modexe2x80x9d).
FIG. 1 gives a schematic representation of the internal architecture adopted in a semiconductor memory device of the prior art. An explanation is next given of the operation when reading in bursts is performed from the memory cell arrays shown in this figure. A read address that is supplied from outside the semiconductor memory device is assumed to correspond to, for example, memory cells inside memory cell array 101U. In this case, the data of, for example, 8 bits (bit 0-bit 7) corresponding to the designated read address are read in parallel from memory cell array 101U and simultaneously supplied to data amplifier 107U. Data amplifier 107U supplies the four bits of even data to parallel-serial conversion circuit 108Ue and the four bits of odd data to parallel-serial conversion circuit 108Uo. 
Parallel-serial conversion circuit 108Ue converts the even data to four bits of serial data by sequentially outputting the received even data to selector 109e in synchronization with the fall of basic clock CLK. Parallel-serial conversion circuit 108Uo similarly converts the odd data to four bits of serial data by sequentially outputting the received odd data to selector 109o in synchronization with the rise of basic clocks CLK. Since data are read from memory cells 101U as described in the foregoing explanation, selectors 109e and 109o select serial data that are supplied from parallel-serial conversion circuits 108Ue and 108Uo in accordance with selection signals U/L.
Multiplexer 110 selects the output of selectors 109e and 109o at the rise of and fall, respectively, of basic clocks CLK, and alternately outputs even data and odd data. The eight bits of serial data from bit 0 to bit 7 are thus outputted to the outside in a burst through an output buffer (not shown in the figure) and input/output pad 100. In addition, read operations from memory cell array 101L are also carried out according to the above-described operation, data in this case being sent through data amplifier 107L and parallel-serial conversion circuits 108Le and 108Lo and from selectors 109e and 109o to multiplexer 110. Since the operation of writing to the memory cell arrays is not directly related to the problem to be solved, explanation is here omitted.
Thus, even if operations take place in accordance with a high-speed clock outside the semiconductor memory device, the read or write process can be carried out inside the semiconductor memory device at a period of eight times this clock because eight bits of data can be outputted to the outside or received from the outside in one instance of reading or writing, as described hereinabove. To describe in more specific terms, the architecture of the read system may be composed of memory cell arrays 101U and 101L and data amplifiers 107U and 107L for low speed; and by: parallel-serial conversion circuits 108Ue, 108Uo, 108Le, and 108Lo; selectors 109e and 109o; multiplexer 110; and input/output pad 100 for high speed. In this case, the length of wiring of the latter path is shorter than that of the former, and there are fewer constituent elements on the latter path than on the former path. As a result, the use of larger transistors has little effect on the size of a chip, making this architecture readily applicable to high-speed operation.
In a typical general-purpose clock-synchronized DRAM, however, there is variation in the locations in the memory cell array or each of the bits of data that are to be read in parallel from the memory cell array. In other words, the locations of all of the bits are distributed over the entire memory cell array with no relation between the bits of parallel data that are read first and the bits that are read last. In the prior art, therefore, processing is carried out by slowing the CPU to match the processing speed of the DRAM. For example, if the CAS (Column Address Strobe) latency is set to xe2x80x9c3,xe2x80x9d the CPU assigns the CAS signal to the DRAM and then waits xe2x80x9c3 cyclesxe2x80x9d before receiving the read data from DRAM. Essentially, read time in the prior art is determined by the bit that takes the most time to read, thereby determining not only the specifications of the DRAM but the design of the system that uses the DRAM. Accordingly, the same level of high-speed access is demanded for all bits from bit 0 to bit 7 in a case in which eight bits of data are read in parallel from a memory cell array.
On the other hand, the type of semiconductor memory device that is taken as the object of the present invention has a fixed burst output as described hereinabove, and the data that are read from a memory cell array are sequentially outputted in a burst of, for example, an eight-bit portion from bit 0 to bit 7. This order of output depends on the various operation modes such as the above-described latch mode or through mode and does not change, and it is determined in advance as a specification that the bit that is to be outputted first is always bit 0.
Accordingly, in a semiconductor memory device having a fixed burst output, the demand for the reading of bit 0 is the most stringent regarding time, and the performance of the semiconductor memory device is governed by how fast this bit 0 is read. In particular, when the semiconductor memory device is operated in through mode, the data of bit 0 that is read from the memory cell array must be transferred xe2x80x9cthroughxe2x80x9d without latching to multiplexer 110 in the vicinity of input/output pad 100. As a result, the timing demand becomes more stringent with increased length of the read path.
In semiconductor memory devices of the prior art, however, consideration is given only to the access of all bits of parallel data within the same general time period, as with general-purpose DRAM, and these devices are not designed with consideration given to high-speed access with special attention to only bit 0. In other words, in semiconductor memory devices of the prior art, conditions regarding the location of each bit in each memory cell array are not taken into consideration, and a configuration is adopted in which even data and odd data are stored mixed within each memory cell array. In semiconductor memory devices of the prior art, for example, the only guarantee is that the access time of a memory cell located at the most remote end with respect to data amplifier 107U (for example, memory cell Cf shown in FIG. 1) will not exceed a prescribed permissible time.
As described above, there is a possibility in the semiconductor memory device of the prior art that the memory cell of bit 0 that is to be outputted first in burst reading is located at the position that is most remote from the data amplifier, as with memory cell Cf shown in FIG. 1, whereby more time will be required for the read data to reach data amplifier 107U than for a case in which the memory cell of bit 0 is located in the vicinity of data amplifier 107U, similar to memory cell Cn of the same figure. This increase in access time causes a problem for the operating speed characteristics.
Although the memory cell array in FIG. 1 is shown spreading in the horizontal direction for the sake of easy depiction, an actual memory cell array takes on a form that is spread out more in the vertical direction of the figure. As the capacity of a semiconductor memory device further increases in the future, moreover, the degree of vertical elongation will inevitably become more pronounced. For example, the length of memory cell array 101U or memory cell array 101L in the vertical direction of the figure (in other words, the distance that is substantially equal to the distance between memory cell Cn and memory cell Cf in FIG. 1) has reached the order of millimeters at the present time. The vertical dimension of the memory cell array is thus now 2 mm (=2000 xcexcm), and, regarding characteristics, the I/O (input/output) lines connecting the data amplifier and sense amplifier (not shown in the figure) are assumed to have a capacitance of 1 pF per millimeter, a width of 1 xcexcm, and a conductivity of 0.05xcexa9 per unit of area.
According to these conditions, a 2-mm portion of wiring has a resistance of 100xcexa9 and a time constant (CR) of approximately 200 ps. This 200 ps is nothing more than the estimated minimum delay when considering only the load of the I/O lines, and, depending on the conditions, the time constant may reach as high as 500 ps. Further, the load of the I/O lines increases and the delay time grows in proportion to increase in the scale of each memory cell array as the capacity of the semiconductor memory device is increased. If the various causes of delay other than the load of the I/O lines are all taken into consideration, including for example, the delay of the address system and the delay for a selection path to reach input/output pad 100 from data amplifier 107U, a total delay of nearly 1 ns is conceivable. Considering that the access time of current semiconductor memory devices is several ns, a delay of nearly 1 ns cannot be ignored.
Although even data and odd data are stored mixed within each memory cell array in the example shown in FIG. 1, another example may be considered in which only even data are stored in memory cell array 101U and only odd data are stored in memory cell array 101L. However, even when such a construction is adopted, the above-described problems still occur without change despite the minor alteration of the configuration of such components as the data amplifiers, write amplifiers, serial-parallel conversion circuits, and parallel-serial conversion circuits. The same problems occur because, in this configuration as well, memory cells such as memory cell Cf that are located at the most remote end with respect to data amplifier 107U still exist in memory cell array 101U, in which even data including bit 0 are stored.
Theoretically, a configuration other than the above-described configurations can also be considered in which each memory cell array is further divided so as to lighten the load of I/O lines, and peripheral circuits such as write amplifiers, data amplifiers, serial-parallel conversion circuits, and parallel-serial conversion circuits are provided for each of the subdivided memory cell arrays. However, the serial-parallel conversion circuits and parallel-serial conversion circuits constitute huge circuit blocks, and the adoption of such a configuration would only decrease the amount of space occupied by cells, making this configuration an extremely unrealistic solution.
The present invention was achieved in view of the above-described state and has as an object the provision of a semiconductor memory device that, despite increase in the size of each memory cell array that accompanies increased capacity of a semiconductor memory device, can output the first data of serial data that are read in bursts to the outside at high speed, and that can reduce the consumption of electrical power.
The semiconductor memory device of the present invention is a semiconductor memory device that is provided with an output means that sorts into a prescribed order a plurality of bits of data that have been read from a memory sub-array having a plurality of memory cells and continuously outputs to the outside; wherein memory cells in which bits of data that are to be outputted first are stored are arranged such that bits of data that are to be outputted first can be outputted to the output means in a shorter time than bits of data that are simultaneously outputted.
According to a first aspect, a memory sub-array is divided into a plurality of memory cell arrays; and of the plurality of bits of data, the bits of data that are to be outputted first are stored in a first memory cell array of the plurality of memory cell arrays; this first memory cell array being arranged closer to the output means than the other memory cell arrays.
The memory sub-array may be constituted by the first memory cell array and a second memory cell array; and regarding the plurality of bits of data that are to be read simultaneously, the bits of data that are to be outputted first may be stored in the first memory cell array and the remaining bits of data may be alternately stored in a prescribed order in the two memory cell arrays; and when reading, each of the bits of data may be alternately read from the first memory cell array and the second memory cell array and outputted continuously to the outside, with the first memory cell array, in which are stored the bits of data that are to be read first, being read first. Each of the bits of data that are alternately read from the first memory cell array and second memory cell array may be alternately outputted to the outside in synchronization with the rise and fall of clocks, and the bits of data that are to be outputted first may be read from the first memory cell array and transmitted xe2x80x9cthroughxe2x80x9d as far as the output terminal.
According to a second aspect, the length of a first output line, which is for reading from the memory sub-array the bits of data that are to be outputted first of the plurality of bits of data and transmitting to the output means, is shorter than other output lines for transmitting to the output means other bits of data that are simultaneously outputted.
The first output lines and the other output lines are hierarchical output lines that are made up by: local output lines onto which are read bits of data that are stored in the memory cells; and global output lines for transmitting to the output means bits of data that have been read onto the local output line; and the length of global output lines that make up the first output lines may be shorter than the length of global output lines that make up the other output lines.
Alternatively, the memory sub-array may be made up by a plurality of memory cell arrays; each of the memory cell arrays may be further made up by a plurality of memory cell plates; local output lines may be provided for each group of a prescribed number of memory cell plates that are arranged adjacent to each other; and global output lines may be arranged to lead from each of the groups of local output lines to the output means; or, local output lines may be provided for each memory cell plate, and global output lines may be provided to lead from each of the local output lines to the output means; and, of the plurality of local output lines for transmitting to global output lines bits of data that are simultaneously outputted, the local output lines for transmitting the bits of data that are to be outputted first are preferably arranged closest to the output means.
According to a third aspect, the memory sub-array is divided into a plurality of memory cell arrays, and at the time of reading the plurality of bits of data that are read, only those areas in which this plurality of bits of data are stored are activated and the prescribed bits of data are read.
The semiconductor memory device may be provided with a plurality of memory sub-arrays and the plurality of bits of data that are to be read may be stored in memory cell arrays of the plurality of memory sub-arrays; and at the time of reading this plurality of bits of data, only those memory sub-arrays in which the plurality of bits of data are stored may be simultaneously activated and the prescribed bits of data read; or, the plurality of bits of data that are to be read may be stored in the memory cell arrays of a single memory sub-array, and at the time of reading this plurality of bits of data, only the memory cell arrays in which this plurality of bits of data are stored are simultaneously activated and the prescribed bits of data are read; or, each of the plurality of memory cell arrays may be further divided into a plurality of areas that are independently activated, and at the time of reading the plurality of bits of data, only the areas of the memory cell arrays in which the plurality of bits of data are stored may be activated, and the prescribed bits of data read.
The above and other objects, features, and advantages of the present invention will become apparent from the following description based on the accompanying drawings which illustrate an example of a preferred embodiment of the present invention.